1. Field of the Invention
The present invention relates to a double data rate memory device, and more particularly, to a double data rate memory device having a data selection circuit and different input/output (I/O) data paths.
2. Description of the Related Art
Generally, a delay locked loop (DLL) circuit is used in a synchronous semiconductor memory device, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), to perform synchronization between an internal clock signal and an external clock signal of the synchronous semiconductor memory device. When the external clock signal is connected to the synchronous semiconductor memory device, a time delay occurs due to a clock skew between the external clock signal and the internal clock signal. Therefore, the DLL circuit is employed in the synchronous semiconductor memory device for generating the synchronized internal clock signal by compensating the clock skew.
FIG. 1 shows a block diagram of a typical analog DLL circuit 10. The analog DLL circuit 10 includes a delay line 12 including a plurality of delay cells. A phase detector 16 receives an external clock signal ECLK and an output clock signal DQS and detects the phase difference between the two clock signals ECLK and DQS. A charge pump circuit 18 provides a control voltage VC to vary the delay time of the delay line 12 according to the comparison result of the phase detector 16. A logic circuit 14 generates pulse signals Z1 and Z2 prior to rising and falling edges of a clock signal from the delay line 12. As such, the DLL circuit 10 generates and outputs the internal clock signal DQS delayed from the external signal ECLK to the DDR SDRAM, and the DDR SDRAM processes I/O data (also referred to as DQ signals) using both rising and falling edges of the clock signal DQS, which functions as a data strobe to control the timing of data transfer.
FIG. 2 shows a simplified block diagram of a memory device 200. The memory device 200 includes a memory cell array 202. The memory cell array 202 typically includes a dynamic random access memory (DRAM) which includes a plurality of memory cells arranged in a matrix. A row decoder 204 and a column decoder 206 access individual memory cells in the matrix in response to an address, provided on an address bus. Multiple input circuits 210-212 and multiple output circuits 214-216 connected to data buses 218 0-N transfer bi-directional data to the memory cell array 202. Each of the data buses 218 0-N provides a plurality of bits of data D0-DN. In addition, a clock generator 208, including the aforementioned DLL circuit, generates various clock signals for controlling the timing of the memory device 200.
As shown in FIG. 2, the memory device 200 includes the plurality of data buses 218 0-N for data communication with the memory cell array 202. FIG. 3 shows a data transfer mechanism between a main memory and a data bus disclosed in U.S. Pat. No. 6,504,767. Referring to FIG. 3, the data bus includes a first output path 302 and a second output path 304. Each of the data paths transfers first and second data bits from a main memory to a data pad DQ0 in one clock cycle during a read operation. In the first output path 302, data transferred to a latch node A is controlled by MUX 320 and MUX 322, which receive clock signals CLKA and CLKB, respectively. In the second output path 304, data transferred to a latch node B is controlled by MUX 324 and MUX 326, which also receive clock signals CLKA and CLKB, respectively. In this case, the clock signals CLKA and CLKB are activated according to the initial address of a column of the main memory. Because each data bus requires two output paths for transmitting data based on the address of the column, the wire routing in this configuration is extensive and complex.
Therefore, there is a need to provide a double data rate memory device with fewer data paths for transferring data during a read and write operation. Specifically, the double data rate memory device has a data selection circuit for reducing the number of data lines and has two data paths connected to the data selection circuit for transferring the data.